Add checks for SIMD

libbuild2-autoconf/libbuild2/autoconf/checks/HAVE_AVX.h

@@ -0,0 +1,14 @@
+// HAVE_AVX
+
+#undef HAVE_AVX
+
+/* GCC, Clang: -mavx
+ *
+ * MSVC: /arch:{AVX,AVX2,AVX512}
+ *
+ * This code is based on
+ * https://code.qt.io/cgit/qt/qtbase.git/tree/src/corelib/global/qsimd.h.
+ */
+#ifdef __AVX__
+#  define HAVE_AVX 1
+#endif

libbuild2-autoconf/libbuild2/autoconf/checks/HAVE_AVX2.h

@@ -0,0 +1,14 @@
+// HAVE_AVX2
+
+#undef HAVE_AVX2
+
+/* GCC, Clang: -mavx2
+ *
+ * MSVC: /arch:{AVX2,AVX512}
+ *
+ * This code is based on
+ * https://code.qt.io/cgit/qt/qtbase.git/tree/src/corelib/global/qsimd.h.
+ */
+#ifdef __AVX2__
+#  define HAVE_AVX2 1
+#endif

libbuild2-autoconf/libbuild2/autoconf/checks/HAVE_SSE.h

@@ -0,0 +1,21 @@
+// HAVE_SSE
+
+#undef HAVE_SSE
+
+/* GCC, Clang: -msse
+ *
+ * MSVC (x86):    /arch:{SSE,SSE2,AVX,AVX2,AVX512}
+ * MSVC (X86-64): Always enabled
+ *
+ * This code is based on
+ * https://code.qt.io/cgit/qt/qtbase.git/tree/src/corelib/global/qsimd.h.
+ */
+#ifdef _MSC_VER
+#  if defined(_M_X64) || (defined(_M_IX86_FP) && _M_IX86_FP >= 1)
+#    define HAVE_SSE 1
+#  endif
+#else
+#  ifdef __SSE__
+#    define HAVE_SSE 1
+#  endif
+#endif

libbuild2-autoconf/libbuild2/autoconf/checks/HAVE_SSE2.h

@@ -0,0 +1,21 @@
+// HAVE_SSE2
+
+#undef HAVE_SSE2
+
+/* GCC, Clang: -msse2
+ *
+ * MSVC (x86):    /arch:{SSE2,AVX,AVX2,AVX512}
+ * MSVC (X86-64): Always enabled
+ *
+ * This code is based on
+ * https://code.qt.io/cgit/qt/qtbase.git/tree/src/corelib/global/qsimd.h.
+ */
+#ifdef _MSC_VER
+#  if defined(_M_X64) || (defined(_M_IX86_FP) && _M_IX86_FP >= 2)
+#    define HAVE_SSE2 1
+#  endif
+#else
+#  ifdef __SSE2__
+#    define HAVE_SSE2 1
+#  endif
+#endif

libbuild2-autoconf/libbuild2/autoconf/checks/HAVE_SSE3.h

@@ -0,0 +1,20 @@
+// HAVE_SSE3
+
+#undef HAVE_SSE3
+
+/* GCC, Clang: -msse3
+ *
+ * MSVC: /arch:{AVX,AVX2,AVX512}
+ *
+ * This code is based on
+ * https://code.qt.io/cgit/qt/qtbase.git/tree/src/corelib/global/qsimd.h.
+ */
+#ifdef _MSC_VER
+#  ifdef __AVX__
+#    define HAVE_SSE3 1
+#  endif
+#else
+#  ifdef __SSE3__
+#    define HAVE_SSE3 1
+#  endif
+#endif

libbuild2-autoconf/libbuild2/autoconf/checks/HAVE_SSE4_1.h

@@ -0,0 +1,20 @@
+// HAVE_SSE4_1
+
+#undef HAVE_SSE4_1
+
+/* GCC, Clang: -msse4.1
+ *
+ * MSVC: /arch:{AVX,AVX2,AVX512}
+ *
+ * This code is based on
+ * https://code.qt.io/cgit/qt/qtbase.git/tree/src/corelib/global/qsimd.h.
+ */
+#ifdef _MSC_VER
+#  ifdef __AVX__
+#    define HAVE_SSE4_1 1
+#  endif
+#else
+#  ifdef __SSE4_1__
+#    define HAVE_SSE4_1 1
+#  endif
+#endif

libbuild2-autoconf/libbuild2/autoconf/checks/HAVE_SSE4_2.h

@@ -0,0 +1,20 @@
+// HAVE_SSE4_2
+
+#undef HAVE_SSE4_2
+
+/* GCC, Clang: -msse4.2
+ *
+ * MSVC: /arch:{AVX,AVX2,AVX512}
+ *
+ * This code is based on
+ * https://code.qt.io/cgit/qt/qtbase.git/tree/src/corelib/global/qsimd.h.
+ */
+#ifdef _MSC_VER
+#  ifdef __AVX__
+#    define HAVE_SSE4_2 1
+#  endif
+#else
+#  ifdef __SSE4_2__
+#    define HAVE_SSE4_2 1
+#  endif
+#endif

libbuild2-autoconf/libbuild2/autoconf/checks/HAVE_SSSE3.h

@@ -0,0 +1,20 @@
+// HAVE_SSSE3
+
+#undef HAVE_SSSE3
+
+/* GCC, Clang: -mssse3
+ *
+ * MSVC: /arch:{AVX,AVX2,AVX512}
+ *
+ * This code is based on
+ * https://code.qt.io/cgit/qt/qtbase.git/tree/src/corelib/global/qsimd.h.
+ */
+#ifdef _MSC_VER
+#  ifdef __AVX__
+#    define HAVE_SSSE3 1
+#  endif
+#else
+#  ifdef __SSSE3__
+#    define HAVE_SSSE3 1
+#  endif
+#endif

libbuild2-autoconf/libbuild2/autoconf/checks/HAVE_XOP.h

@@ -0,0 +1,15 @@
+// HAVE_XOP
+
+#undef HAVE_XOP
+
+/* GCC, Clang: -mxop
+ *
+ * MSVC: No controlling compiler option nor indicating macro. The
+ *       documnetation is murkily says it's always enabled on AMD and only AMD
+ *       processors; see:
+ *       https://docs.microsoft.com/en-us/cpp/intrinsics/x86-intrinsics-list
+ *       https://docs.microsoft.com/en-us/cpp/intrinsics/x64-amd64-intrinsics-list)
+ */
+#ifdef __XOP__
+#  define HAVE_XOP 1
+#endif